20 publicaciones de empleo destacadas de lead electrical engineer en madrid, md (¡Están contratando!)

Senior Formal Verification Engineer
TechBiz Global GmbH —Madrid, Madrid provincia
- Jornada completa
- Teletrabajo
- Microsoft Word
- Doctorado
- Informática
Solicitud rápida
Piping Engineer (Construction)
Dapin —San Sebastián de los Reyes, Madrid provincia
- Inglés
- Oficina
TCMS Engineer – Central vehicle control
Siemens —Tres Cantos, Madrid provincia
- Jornada completa
- Trabajo híbrido
- Informática
- Inglés
- Grado
Junior Project Assurance Engineer - Rail Mobility
Siemens —Tres Cantos, Madrid provincia
- Jornada completa
- Trabajo híbrido
- Inglés
- Grado
- Negociación
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Solutions & Execution Engineer
Toyota Automated Logistics —Madrid, Madrid provincia
- Jornada completa
- Inglés
- Máster
- Grado
MEP Project/Design Manager - Barcelona/Madrid
Bryden Wood —Madrid, Madrid provincia
- Trabajo híbrido
- Español
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Microwave Instrument System Engineer
Airbus Defence and Space SAU —Getafe, Madrid provincia
- Jornada completa
- Trabajo híbrido
- Español
- Inglés
Software Engineer – Train Traction & Control Systems
Siemens —Tres Cantos, Madrid provincia
- Jornada completa
- Trabajo híbrido
- Informática
- Inglés
- Desarrollo de software
Senior FPGA Engineer — Wireless Networking Group (WNG)
IMDEA Networks Institute —Madrid, Madrid provincia
- Español
- Doctorado
- Informática
1d
Junior Electronics Engineer
Destinus —Madrid, Madrid provincia
- Jornada completa
- AutoCAD
- Español
- Inglés
Solicitud rápida
System Development Engineer, WW AMZL In House Controls, In-House Controls, World-Wide Central Engineering
Amazon EU SARL (Spain Branch) —Madrid, Madrid provincia
- Jornada completa
- Inglés
- Java
- C++
BESS Engineering Director, Global
Enfinity Global —Madrid, Madrid provincia
- Jornada completa
- Máster
- Grado
- Ingeniería eléctrica
- Vacaciones pagadas
Solicitud rápida
Associate Director – T&D Protection & Control Substations
AECOM —Madrid, Madrid provincia
- Jornada completa
- Trabajo híbrido
- AutoCAD
- Grado
- Ingeniería eléctrica
- Seguro dental
- Vacaciones pagadas
System Engineer (m/f/d) Brake Systems for Rail Vehicles
Siemens —Tres Cantos, Madrid provincia
- Jornada completa
- Trabajo híbrido
- Español
- Inglés
- Máster
Project Engineer – Water Treatment (f/m/d)
Arcadis —Madrid, Madrid provincia
- Jornada completa
- Español
- Inglés
- Máster
Senior System Engineer - On-Board ATP (High-Speed Rail)
Siemens —Tres Cantos, Madrid provincia
- Jornada completa
- Trabajo híbrido
- Inglés
- Máster
- Ingeniería eléctrica
SIM Engineer II
Cubic³ —Madrid, Madrid provincia
- Jornada completa
- Trabajo híbrido
- Informática
- Java
- SQL
Technical Support Engineer
Sandvik —San Fernando de Henares, Madrid provincia
- Jornada completa
- Ventas
- Inglés
Process Safety Engineer
Dapin —San Sebastián de los Reyes, Madrid provincia
- Inglés
- Oficina
CSM Chemfeed Project Engineer
Water Technologies —Rivas-Vaciamadrid, Madrid provincia
- Jornada completa
- Trabajo híbrido
- AutoCAD
- Project management
Solicitud rápida

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Senior Formal Verification Engineer

TechBiz Global GmbH
Madrid, Madrid provincia

Solicitud rápida

Detalles del empleo

Jornada completa

Cualificaciones

Microsoft Word
Doctorado
Informática
Máster
Bash
Grado
Scripting
Python
Shell Scripting

Descripción completa del empleo

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Solicitud rápida

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