Role summary
Own verification of the Load/Store Unit, data cache and bus interfaces for a CPU/GPU core — the block handling memory ordering, address generation, cache/TLB interaction, forwarding, and exception handling. Contribute to drive the LSU from RTL freeze to tapeout-quality sign-off.
Responsibilities-
Define and own the LSU verification plan: functional coverage, testplan, checkers, and closure criteria
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Build/extend UVM testbench components for LSU (drivers, monitors, scoreboards, memory models)
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Develop directed and constrained-random tests covering store-to-load forwarding, memory ordering (RISC-V WMO model), speculative loads, vector accesses, misaligned/split accesses, exceptions/faults, and pipeline hazards
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Drive formal verification for ordering/coherence properties where simulation coverage is weak
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Debug RTL/testbench failures in collaboration with design; triage and root-cause
Track and close functional/code coverage; report verification status to program - s
Mentor- verification engineers; review testbench code and testplans
Interface with architecture, design, and DV - s on other units to resolve cross-unit issues.
Why Seynamics?-
Work at one of Europe's most promising deep-tech semiconductor scale-ups.
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Accelerated development path.
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4 days per week in the Barcelona office (city center), 1 WFH day.
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1 week of work from everywhere in the world.
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Competitive package.
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A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.
