We are seeking a Senior or Principal Verification Engineer to assume ownership of our core (top-level) testbench, along with the verification methodology, tooling, and continuous integration infrastructure that support it. In this role, you will be responsible for evolving the top-level UVM environment, integrating unit-level verification IP, driving functional and code coverage closure across the core, and identifying verification gaps at the boundaries between units. You will also serve as a technical er within the organization, contributing to the company-wide initiative to advance AI-powered verification methodology. This position requires a rigorous, detail-oriented approach to verification and the ability to provide technical guidance and mentorship to engineers across the design verification organization.
Key Responsibilities-
Core testbench ownership — Own, improve, and continuously evolve the top-level core testbench and its UVM environment. Extend the testsuites, and integrate all the unit-level VIPs so block-level checkers, monitors, and coverage are reused at top level.
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Coverage — Own functional and code coverage at the core level: review the nightly results, drive closure across units, and audit covergroups and tests for real quality and intent.
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Cross-unit gap hunting — Find and close verification holes at the boundaries between units. Reconcile assume/guarantee relationships across unit testbenches: e.g., everything one module assumes about surrounding modules, needs to be verified by surrounding modules' testbenches.
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Methodology, tooling & CI — Own the verification flows (compile, coverage collection, regression) and the CI as the core RTL evolves: update compile configs, retire stale jobs, create new ones, keep regressions healthy and efficient. Drive concrete upgrades — migrate our scripts and flows to latest versions (e.g., start using Questa One and next-generation coverage, from Siemens, instead of the old flow) — and stay in regular contact with EDA vendors to keep us on the latest capabilities.
Technical ership & mentorship — Act as the- technical reference for core verification engineers, review block- and core-level testbench architectures, and mentor on coverage-driven and assertion-based verification.
Why Seynamics?-
Work at one of Europe's most promising deep-tech semiconductor scale-ups.
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Accelerated development path.
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4 days per week in the Barcelona office (city center), 1 WFH.
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1 week of work from everywhere in the world.
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Competitive package.
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A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.
