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Verify digital logic using SystemVerilog and reusable, standardized methodologies. Verify digital systems that use both custom and standard IP components and interconnects, including microprocessor cores and hierarchical memory subsystems.
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Contribute to verification and modeling at the chip top level.
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Debug tests with design engineers to deliver functionally correct design blocks. Work closely with the design and test teams to define test specifications, verification plans and manufacturing transfer.
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Create and maintain verification infrastructure and tools.
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Collect and analyze coverage metrics and establish verification best practices.
Required title: MSc in Electronic, Electrical, Computer Engineering or relevant field
Required expertise: at least 3 years in similar tasks.
Knowledge and Skills
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Experience in the verification of designs such as transceivers ICs and System on Chip (SoC).
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Experience with industry-standard simulators, revision control systems and regression systems.
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Experience with Verilog, SystemVerilog, SVA and functional coverage and working knowledge of makefiles and scripting languages, such as Perl or Python.
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Experience with verification of low power techniques.
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Experience with UPF flow.
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Familiarity with SoC standard interfaces (e.g. AHB, APB) and memory system architectures.
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Proven software skills
